Category: PCI-Express
tool:-
Device: Stratix® V


Set to Preset 7 or 8.
For example in a Gen3 x8 Avalon-ST design:

top > synthesis > submodules
File name: altpcie_sv_hip_ast_hwtcl.v

Please check below line 1376.
↓
localparam [17:0] gen3_coeff_1 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_1_hwtcl [17:0]: 18'h7;
...
localparam [17:0] gen3_coeff_2 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_2_hwtcl [17:0]: 18'h8;
...
localparam [17:0] gen3_coeff_3 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_3_hwtcl [17:0]: 18'h7;
...
localparam [17:0] gen3_coeff_4 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_4_hwtcl [17:0]: 18'h8;

It is possible to change the Preset value, but please note that the optimal value will differ depending on the characteristics of the channel.
Please edit by referring to the following Knowledge Database.

(Reference) How to set up the Stratix V PCIe HIP to request preset 9 to improve its Gen 3 receive eye margin?
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd01232015_198.html