Category: Simulation
Tools: ModelSim® / Quartus® Prime
device:-

<Error message>
Error: //<altclkctrl_ip_name>/simulation/submodules/<altclkctrl_ip_name>_altclkctrl_0.vhd(148): near "BEGIN": (vcom-1576) expecting END.

There is a bug in the VHDL simulation model for the ALTCLKCTRL IP that causes an error when compiled in a simulator such as ModelSim.
If an error similar to the above occurs, avoid it by following the steps below.

・Target device: ALL FPGA
・Applicable tools: Pro 19.1 / Standard 18.1 / Lite 18.1

[Problem factor]
[Pro Edition]
//<altclkctrl_ip_name>/altclkctrl_*/sim/<altclkctrl_ip_name>_altclkctrl_*_*.vhd

There is no END COMPONENT declaration for <altclkctrl_ip_name>_altclkctrl_*_*_sub declared as COMPONENT in the above model.

[Standard/Lite Edition]
//<altclkctrl_ip_name>/simulation/submodules/<altclkctrl_ip_name>_altclkctrl_0.vhd

There is no END COMPONENT declaration for <altclkctrl_ip_name>_altclkctrl_0_sub declared as COMPONENT in the above model.

[Workaround]
Please add the following where applicable.

END COMPONENT;

Then compile in simulator.