Intel: Is there anything I should be careful about when deciding on the placement of the Refclk of the transceiver in Stratix® 10 FPGA?

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Intel: Are there any points to keep in mind when determining the placement of Transceiver's Refclk in a Stratix® 10 FPGA?

PCI Express Quartus Prime Stratix Transceiver

Category: PCI-Express
Tools: Quartus® Prime
Device: Stratix® 10

For reference clock, check below part of the User Guide.

(reference)
Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf
- 1.3.5.2. Input Reference Clock Sources
- 3.2. Input Reference Clock Sources

Also, actually create a sample with Quartus® Prime, place the terminals, and check whether fitting is possible.

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