Intel: On an FPGA board equipped with DDR3, we measured the memory clock and DQA signals with an oscilloscope and performed a tDQSCK JEDEC standard conformance check, but it was found to be significantly outside the range specified in the data sheet and was rejected. The vias directly below the FPGA balls are used as the measurement points, but is this a problem?

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Intel: When I measured the memory clock and DQA signal with an oscilloscope on an FPGA board equipped with DDR3 and checked tDQSCK for JEDEC standard conformance, it greatly deviated from the range specified in the datasheet and was rejected. Is there a problem with using the via directly under the ball of the FPGA as the measurement point?

Category: External memory interface
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Incorrect measurement point. It should be measured on the memory device side.
tDQSCK is described in the JEDEC standard as tDQSCK: "DQS, #DQS rising edge output access time from rising CK, #CK", and the target is the differential CK - difference of I/O pin (ball) of DDR3 SDRAM device. It is the time difference between the edges of dynamic DQS.

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