Category: SoCs
Tools: Quartus® Prime (Platform Designer)
Device: Arria® 10


The Ethernet MAC interface that uses the I/O on the FPGA side of the Arria® 10 SoC supports five types: MII, GMII, RMII, RGMII, and SGMII.
However, when selecting FPGA Routing on Platform Designer, only GMII/MII can be selected.

All except GMII/MII require support to implement adapter logic on the FPGA side.
Especially for RMII, since adapter logic is not provided, it is necessary to make everything yourself.

For details, please refer to the document below.
"Intel Arria 10 Hard Processor System Technical Reference Manual" (a10_5v4 | 2017.07.22)
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_5v4.pdf
(Item of 18.1.5 PHY Interface 14)

Although it is described in the following content, the one described as "∗with additional required adapter logic∗" corresponds to the interface that requires adapter logic.

The PHY interfaces supported using the HPS I/O pins are:

• Reduced Media Independent Interface (RMII)
• Reduced Gigabit Media Independent Interface (RGMII)

The PHY interfaces supported using the FPGA I/O pins are:

• Media Independent Interface (MII)
• Gigabit Media Independent Interface (GMII)
• Reduced Media Independent Interface (RMII) with additional required adapter logic (Note: Additional adapter logic for RMII not provided.)
• Reduced Gigabit Media Independent Interface (RGMII) with additional required adapter logic
• Serial Gigabit Media Independent Interface (SGMII) supported through transceiver I/O or high-speed low-voltage differential signaling (LVDS) with soft clock data recover (CDR) I/O with additional required adapter logic