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Intel: What is the meaning of Inner / Outer that can be selected as a Cache attribute setting for Cyclone® V SoC (Cortex-A9) MMU settings?
SoC FPGAs
Category: SoCs
Tools: Quartus® Prime
Device: Cyclone® V
It is as follows.
- inner cacheability attribute: L1 cache attribute
- outer cacheability attribute: L2 cache attribute
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