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Intel: Is it OK to gate pll_ref_clk at boot time on Stratix® 10? Also, how can I perform recalibration?
Stratix
Category: External memory interface
tool:-
Device: Stratix® 10
pll_ref_clk cannot be gated.
Please connect directly with the input pin.
To execute recalibration, execute local_reset_req under the following conditions.
- Have local_reset_done =1
- The width of High must be at least 2 clk widths of core_clk.
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