Intel: I am implementing PCI-Express (PCIe) on Arria® V GX. When I assign it to a transceiver pin and compile it, an error occurs in the Fitter.

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Intel: Arria® V GX implements PCI-Express (PCIe). An error occurs in the Fitter when I compile by assigning it to a transceiver pin.

PCI Express

<Error message>
Error (14566): Could not place 1 peripheral component(s) due to conflicts with existing constraints (1 Receiver channel(s))
Error (175020): Illegal constraint of Receiver channel that is part of xxx to the region (x, y) to (x, y): no valid locations in region
Category: PCI-Express
Tools: Quartus® Prime
Device: Arria® V

The PCIe Hard IP Block has a fixed layout on the device, and the TX/RX pins and Reset pins are fixed.
(If there are multiple Hard IPs, you can choose which Hard IP Block to use.)
Quartus® Prime automatically assigns the most suitable pins once you compile without pin assignments, so please check.
Note that Refclk can be relocated within the Dedicated pin.

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