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Intel: When co-simulating a circuit generated by the High Level Synthesis (HLS) compiler, when checking the generated wlf file, the frequency of the clock set with --clock is not reflected and is 1 GHz
HLSsimulation
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Category: HLS
Tool: HLS Compiler
device:-
Co-simulation is done to check the latency of the generated circuit, so the clock frequency set with the --clock option is not reflected.
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