Narrow down by specifying conditions
There are currently 4292 hits.
Intel: What is the CM_PLL_CLK1 setting in Table 339. Boot Source MUX Selects in the Reference Manual for Arria® 10 SoC?
Category: SoCs
Tool: Quartus® Prime / SoC EDS
Device: Arria® 10
CM_PLL_CLK[4:0] described in the Intel® Arria® 10 Hard Processor System Technical Reference Manual is a signal for internal test and should not be used by the user.
Intel® Arria® 10 Hard Processor System Technical Reference Manual
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_5v4.pdf
(search for Boot Source MUX Selects)
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.