Category: External memory interface
Tools: Quartus® Prime
device:-


Please note the following points.

・Do not copy the two EMIF IPs, but generate them separately.
However, in the case of Platform Designer, there is no problem in generating two EMIF implementations.
For V series (Stratix® V, Arria® V, Cyclone® V) you need to run pin_assignment.tcl for each EMIF, but copying the EMIF does not generate two pin_assignmnet.tcl.

・Set the Board Skew value of the two EMIF IPs appropriately.
Please note that the two EMIFs may have different FPGA pin-to-memory distances.