Intel: I'm running a PCI-Express (PCIe) design using Stratix® 10. I am using Quartus® Prime v18.1 Pro Edition and am getting Minimum Pulse Width violations during timing analysis.

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Intel: Implements PCI-Express (PCIe) designs with Stratix® 10. I am using Quartus® Prime v18.1 Pro Edition and I am seeing Minimum Pulse Width violations in timing analysis.

Stratix Timing Constraints/Analysis PCI Express Quartus Prime

Category: PCI-Express
Tools: Quartus® Prime
Device: Stratix® 10

Minimum Pulse Width violations as of v18.1 can be ignored.
It will be fixed in a future version, so please wait until then.

(reference)
Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/-why-is-a-minimum-pulse-width-timing -violation-information-messa.html

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