Intel: The clock frequency set with the --clock option in the High Level Synthesis (HLS) compiler is not reflected in the generated SDC file.
HLS
Timing Constraint/Analysis
Category: HLS
Tool: HLS Compiler
device:-
The --clock option is only reflected in the latency and number of resources during RTL conversion, and is not reflected in the SDC file for Quartus® Prime.
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.