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Intel: An error occurs when generating a FIFO (VHDL) from IP Catalog with a data width of 1 bit and simulating it.
<Error message>
Fatal: (vsim-3807) Types do not match between component and entity for port "sample_data".
Category: Simulation
Tools: ModelSim®
device:-
In the generated FIFO description, sample_data is generated with sample_data: IN STD_LOGIC_VECTOR (0 DOWNTO 0); and STD_LOGIC_VECTOR , so if you try to connect with STD_LOGIC in the upper hierarchy, you will get this error due to port mismatch.
When connecting a signal std_logic_vector(0 downto 0) in the lower hierarchy with std_logic in the upper hierarchy in VHDL,
a(0) => b
Add (0) and connect.
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