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Intel: There are Edge and Level interrupt settings for PIO cores in Platform Designer (formerly Qsys). What is the difference?
platform designer
Category: Quartus® Prime (Platform Designer)
Tools: Quartus® Prime
device:-
The behavior of the interrupt signal is different.
- Level: The input signal level becomes the IRQ signal level. (The input signal assertion time becomes the IRQ assertion time.)
- Edge: Continue to assert the IRQ signal when the specified edge is recognized. (until the register is cleared by software)
If Interrupt is set to Edge, Edge capture register must also be used with ON, otherwise Platform Designer will display an error message.
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