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Intel: Is it better to consider the wiring delay inside the package when making equal length wiring for the EMIF pattern?

Stratix Arria

Category: External memory interface
tool:-
Devices: Stratix® 10, Stratix® V, Arria® 10


As described in the following document, it is recommended to consider the wiring delay in the package when designing above (or exceeding) a certain frequency depending on each device and memory protocol.

reference
External Memory Interface Handbook Volume 2: Design Guidelines
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf
(Search for Package Deskew Recommendations.)

・Package Deskew Recommendation for Stratix V Devices
(Example: When exceeding 800MHz with Stratix V, DDR3)

・Package Deskew Recommendations for Arria 10 and Stratix 10 Devices
For Arria 10, Stratix 10 and DDR4/DDR3, it is recommended to operate at the following frequencies or higher.

Single Rank: 933[MHz]
Dual Rank: 800[MHz]
Quard Rank: 667[MHz]



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