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Intel: For Cyclone® V SoC booting, if you choose to configure the FPGA side independently from the Hard Processor System (HPS) side, the completion of FPGA configuration and booting of HPS will operate asynchronously. However, if the HPS side boots first while the FPGA side has not completed configuration, will there be any problems?
Category: SoCs
tool:-
Device: Cyclone® V
Due to the implementation of the HPS bootloader (Preloader), if the FPGA has not been configured yet, some registers will not be initialized, allowing the FPGA and HPS to start up independently. .
The initialization process of the following registers related to the interface between FPGA and HPS is executed only when the FPGA has transitioned to user mode.
- rstmgr.brgmodrst Register (Address: 0xFFD0501C)
- l3regs.remap register (Address: 0xFF800000)
- sysmgr.module Register (Address: 0xFFD08028)
Considering the case where the above register initialization is not executed in the Preloader, by implementing the same register initialization in the software after U-Boot (U-Boot, user application, etc.), booting on the HPS side is possible. It is also possible to correspond to the case where it operates in advance.
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