Intel: There is a description of Maximum Trace Length in the EMIF Layout Guidelines, but does that length include the internal wiring length of the package?
Category: External memory interface
tool:-
device:-
It does not include the internal wiring of the package.
The layout guideline value indicates the ball-to-ball distance between FPGA and memory, and does not include the internal wiring length of the package regardless of whether Package deskew is On/Off.
Also, as long as the timing is met, there is no problem even if the layout guideline requirements are not necessarily met.
(In addition, when entering the Board Skew Parameter of the EMIF IP GUI, add the delay due to the internal wiring length when the Package deskew is On.)
reference
External Memory Interface Handbook Volume 2: Design Guidelines
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf
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