Category: DSP, IP (FIR Compier)
Tools: Quartus® Prime, DSP Builder
device:-


For the same sampling rate and clock frequency, you basically need as many multipliers as there are taps.

For lower sampling rates, where more than an integer ratio difference is required, the process of time division multiplexing takes place, ie, we can save multipliers for half or less of the ratio.
BSP Builder will first generate the RTL in Simulink Simulation, so you will know the number of estimates, but check the compilation results in Quartus® Prime for the final result.