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Intel: There are multiple L1 parity error related interrupts such as cpu0_parityfail and cpu0_parityfail_XXX in Cyclone® V SoC devices.
Category: SoCs
Tools: SoC EDS
Device: Cyclone® V
Using cpu0_parityfail will detect an interrupt from any of the interrupt sources defined by cpu0_parityfail_XXX.
For the meaning of interrupts, please also check the documentation on the ARM side.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407g/Cjaceghh.html
For the list of interrupts, please refer to the following document.
Cyclone V Hard Processor System Technical Reference Manual
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
(Search for GIC Interrupt Map.)
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