Intel: Is there anything I should be careful about when using multiple chip selects with the Hard Processor System (HPS) QSPI controller in Cyclone® V SoC?

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Intel: Are there any precautions to be taken when using multiple chip selects with the Cyclone® V SoC's Hard Processor System (HPS) QSPI controller?

SoC FPGAs

Category: SoCs
Tools: SoC EDS
Device: Cyclone® V

There is an item to specify the number of chip selects of the QSPI controller in the HPS setting of Platform Designer.
After specifying the desired number of chip selects here and recompiling the design, you will need to regenerate the Preloader with the generated handoff files.

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