Intel: How does bit 6:s2f, which is the Reset Manager register of the Hard Processor System (HPS) of Arria® V / Cyclone® V SoC FPGA, behave when set?

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Intel: Arria® V / Cyclone® V SoC FPGA Hard Processor System (HPS) Reset Manager register bit 6:s2f, what does setting do?

SoC FPGA SoC EDS/DS-5

Category: SoCs
Tool: SoC EDS
Device: Arria® V / Cyclone® V

s2f is the bit that manipulates the signal of h2f_rst_n.
Normally, it is output when a Warm Reset is issued on the HPS side, but by setting s2f of miscmodrst to 1, it is possible to operate the h2f_rst_n output to the FPGA while keeping the HPS side running.

reference
Cyclone V HPS Memory Map
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#topic/sfo1410067768606.html

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