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Intel: How do I get the SystemVerilog 'define constants to be recognized correctly throughout my ModelSim® project?
simulation
Category: Simulation
Tools: ModelSim®
device:-
To make ModelSim® recognize 'define constants, do the following:
If you are creating a ModelSim project
- Select the source file you want to specify 'define from the Project window, right click and open the property
- Select the Verilog & SystemVerilog tab and click Macro... in Other Verilog Options
- Register individually in the Define Macro window
If you are using Quartus® Prime NativeLink
- From the Tool bar of ModelSim, select Compile ⇒ Compile Options...
- Select the Verilog & SystemVerilog tab and click Macro... in Other Verilog Options
- Register individually in the Define Macro window
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