For Intel: Cyclone® V SoC / Arria® V SoC, is it possible to perform FPGA configuration after starting Linux from the Hard Processor System (HPS) side for an FPGA design that uses the FPGA2SDRAM (F2S) port?

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Intel: For Cyclone® V SoC / Arria® V SoC, is it possible to configure the FPGA after starting Linux from the Hard Processor System (HPS) side for the FPGA design that uses the FPGA2SDRAM(F2S) port?

SoC FPGAs

Category: SoCs
Tools: SoC EDS
Device: Arria® V, Cyclone® V

Setting the applycfg bit from Linux is not supported because the function to set the applycfg bit is implemented in Uboot, and setting the applycfg bit has a restriction that the SDRAM must be in an idle state.

FogBugz #158537: Updating U-Boot FPGA2SDRAM driver
https://github.com/altera-opensource/u-boot-socfpga/commit/75905816ec95b0ccd515700b922628d7aa9036f8

If you need to perform FPGA configuration on Linux, please do so after performing FPGA configuration and setting the applycfg bit once with Uboot.

An example is how to run the unzip command in Uboot.
Add the following to include/configs/socfpga_common.h of Uboot and build,
#define CONFIG_CMD_UNZIP
　
Issue the following command in Uboot.
fatload mmc 0 0x2000000 your_rbf.gz unzip 0x2000000 0x2800000
fpga load 0 0x2800000 $filesize

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