Category: SoCs
Tools: SoC EDS
Device: Cyclone® V


DEFLAGs (cpu0/1_defrags0~6) are exception interrupts caused by the floating point unit (NEON/FPU).
It is described in "Table A-24 Exception flags signals" at the link below.
http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/ada1443777343290.html

DEFLAGSn[6:0]

• Bit6 gives the value of FPSCR27
• Bit5 gives the value of FPSCR7
• Bits[4:0] give the value of FPSCR[4;0]”

Each bit of DEFLAGs is assigned to a specific bit in the FPSCR (Floating-Point Status and Control Register). The FPSCR specification is described in the floating point unit (NEON or FPU) manual.

Cortex-A9 NEON Media Processing Engine Technical Reference Manual
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0409i/Chdfifdc.html
Cortex-A9 Floating-Point Unit Technical Reference Manual
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0408i/Chdfifdc.html

FPSCR[31:0]

• Bit27 QC Set to 1 if Advanced SIMD integer saturation has occurred since 0 was last written to this bit. *
• Bit7 IDC input denormalization cumulative exception flag*
• Bit4 IXC Inaccurate cumulative exception flag*
• Bit3 UFC underflow cumulative exception flag*
• Bit2 OFC Overflow accumulation exception flag*
• Bit1 DZC Accumulated exception flag for division by 0*
• Bit0 IOC Invalid operation cumulative exception flag*

*) Exception flags FPSCR bits 27, 7, and 4:0 are exported to the DEFLAGS output so they can be monitored externally to the processor if desired.

This content is the same for Arria® V SoC and Arria® 10 SoC.

Cyclone® V Hard Processor System Technical Reference Manual
https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html
(Search for GIC Interrupt Map.)