Intel: Regarding the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, which register should I use to control the notification destination (CPU0 or CPU1) of each interrupt?

Narrow down by specifying conditions

現在 4334 件がヒットしています。

Intel: Regarding the interrupt controller (GIC) on the Hard Processor System (HPS) side of Cyclone® V SoC, which register should be used to control the notification destination (CPU0 or CPU1) of each interrupt?

SoC FPGAs

Category: SoCs
Tool: SoC EDS
Device: Cyclone® V

It is possible to specify the CPU of the interrupt notification destination with the following register.

PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0416b/Beifbdhg.html
(3.2.10. Target Registers (ICDIPTRn))

8 bits are mapped to one GIC interrupt, but only bit0 and bit1 are valid (meaning CPU0 and CPU1) and bit2:7 are reserved.

CPU0 only: 0x01
CPU1 only: 0x02
Both CPU0 and 1: 0x03 (*)

(*) PPI interrupt (Private Peripheral Interrupt) can be notified to both CPUs, but SPI interrupt (Shared Peripheral Interrupt) is not guaranteed to be notified to both CPUs. If one CPU clears its pending interrupt first, the other CPU will not be notified of the interrupt.

This content is the same for Arria® V SoC and Arria® 10 SoC.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search