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Intel: For the Interrupt Controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, the reference manual only lists interrupt sources from interrupt number 32 onwards. Are the interrupt numbers 0-31 not assigned to anything?
Category: SoCs
Tools: SoC EDS
Device: Cyclone® V
GIC numbers 32 and higher map interrupts from peripherals shared by CPU0 and CPU1 called SPI (Shared Peripheral Interrupts).
GIC numbers 0 to 31 are independent interrupt factors for CPU0 and CPU1.
For GIC numbers (IDs) 0 to 31, see "3.1.2. Interrupt Distributor interrupt sources" in the Cortex-A9 MPCore Technical Reference Manual.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407g/CCHCEDJC.html
It has the following mapping. (* Nothing is mapped to ID16-26.)
ID0-15: Software Generated Interrupts (SGI) ... software interrupts
ID27: Global timer, PPI ....... Global timer interrupt (Cortex-A9 built-in timer)
ID28: A legacy nFIQ pin, PPI ... Interrupt input to nFIQ pin (*not supported)
ID29: Private timer, PPI ....... Private timer interrupt (Cortex-A9 built-in timer)
ID30: Watchdog timers, PPI ..... Watchdog timer interrupt (Cortex-A9 built-in timer)
ID31: A legacy nIRQ pin, PPI ... interrupt input to nIRQ pin (*not supported)”
This content is the same for Arria® V SoC and Arria® 10 SoC.
Cyclone® V Hard Processor System Technical Reference Manual
https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html
(Search for GIC Interrupt Map.)
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