Intel: I am running Arria® 10's fPLL in feedback_compensation mode, but the fPLL's pll_locked signal and the Transceiver Reset Controller IP's tx_ready signal are low and the PLL does not work.

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Intel: I have an Arria® 10 fPLL running in feedback_compensation mode, but the pll_locked signal of the fPLL and the tx_ready signal of the Transceiver Reset Controller IP are low and the PLL is not running.

Arria Clock/PLL IP

Category: Transceiver
tool:-
Device: Arria® 10

It is necessary to perform the Steps to recalibrate the PLL after power up calibration described in the document below.

Intel Arria 10 Transceiver PHY User Guide
https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html
(Steps to recalibrate the PLL after power up calibration)

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