Category: Specifications
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device:-


Information on wiring delay in the package can be downloaded by clicking Net Length Information for each device from the Net Length Reports link below.
https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html#tools-models-and-libraries

It is also possible to display the information on the routing delay in the package for DQ/DQS pins and Address/Command pins in the report.
For example, if you are designing with Arria® 10, you need to enable the following options in the IP's Arria® 10 External Memory Interfaces.

Board Timing tab:

• FPGA DQ/DQS Package Skews Deskewed on Board
• FPGA Address/Command Package Skews Deskewed on Board

By enabling this, the wiring delay value inside the package is reported to the item called Package Delay in the .pin file.