Intel: Regarding the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, is it possible to specify the interrupt sense polarity for the interrupt signals (FPGA_IRQ0-63) from the FPGA side?

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Intel: For Cyclone® V SoC Hard Processor System (HPS) side Interrupt Controller (GIC), is it possible to specify interrupt sense polarity for interrupt signals (FPGA_IRQ0-63) from FPGA side?

SoC FPGAs

Category: SoCs
tool:-
Device: Cyclone® V

FPGA_IRQx does not support polarity selection by register settings on the HPS side.
Prepare an interrupt signal based on the assumption that it will be detected at the rising edge (positive edge) for Edge and at the High level for Level.

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