Category: SoCs
Tools: SoC EDS
Device: Cyclone® V


As a result of verification on the evaluation board, it was confirmed that the AS configuration on the FPGA side can be re-executed by the following procedure.
This can be handled by controlling the following registers of the FPGA Manager on the HPS side.

fpgamgrregs.ctrl register (Address: 0xFF706004)
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#topic/sfo1410067797617.html

<Procedure>

1. Set MSEL to AS mode in advance
2. Set the en bit (bit0) in the fpgamgrregs.ctrl register to 0x1. This allows control of nCONFIG from FPGA Manager.
3. Set the nconfigpull bit (bit2) in the fpgamgrregs.ctrl register to 0x1. As a result, nCONFIG is pulled down and the FPGA side transitions to Reset state.
4. Set the nconfigpull bit back to 0x0. nCONFIG PULL DOWN is released, the FPGA side is reconfigured, and transitions to user mode.

(Although it is possible to reconfigure the FPGA using the above procedure, it should be noted that the HPS cannot access the FPGA during the reconfiguration. Disable the H2F and LWH2F bridges once. It is necessary to take measures such as