- Semiconductor BusinessHOME
- Products and Services of Macnica,Inc.
-
technical information
-
Events and Seminars
- Handling Manufacturer
- Support
- Inquiry
- Click here to purchase products
- Semiconductor business e-mail magazine registration
Narrow down by specifying conditions
There are currently 4341 results.
Intel: Does the SW_RESET sequence continue to run after releasing the hardware reset signal in the Triple Speed Ethernet (TSE) IP?
Category: IP (Ethernet)
tool:-
device:-
A hardware reset does not execute a sequence like a software reset, and all TSE logics are forcibly initialized by inserting 3 cycles of reset.
Please also refer to the User Guide.
reference
Triple-Speed Ethernet Intel FPGA IP User Guide
https://www.intel.com/content/www/us/en/programmable/documentation/bhc1410932355850.html
(Search for MAC Reset or Clock and Reset Signal.)
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.