Intel: Is there a regulation for controlling HPS_nPOR and HPS_nRST in Arria® 10 SoC?

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Intel: Are there any rules for controlling HPS_nPOR and HPS_nRST for Arria® 10 SoC?

Arria SoC FPGA SoC EDS/DS-5

Category: SoCs
Tool: SoC EDS
Device: Arria® 10

You must comply with the following regulations.

HPS cold reset pulse width 600ns(Min)
HPS warm reset pulse width 600ns(Min)

(reference)
Intel® Arria® 10 Device Datasheet
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_datasheet.pdf
(Search for HPS Reset Input Requirements.)

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