Intel: When accessing the PHY from the EMAC controller of the Hard Processor System (HPS), specify the address in 5 bits of gr[10:6], but what if the PHY has a 16-bit extended register? Should I access it?

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Intel: When accessing the PHY from the EMAC controller of the Hard Processor System (HPS), the address is specified in 5 bits of gr[10:6], but what if the PHY has a 16-bit extended register? should I access the

SoC FPGAs

Category: SoCs
Tool: SoC EDS
Device: Cyclone® V

It is accessed using the two IEEE defined PHY side registers Register13(Dh)/Register14(Eh).

IEEE-Defined Registers
Dh : MMD Access – Control
Eh : MMD Access – Register/Data

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