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Intel: Why is the Warm Reset (HPS_nRST) signal periodically output from the Hard Processor System (HPS) side when the Preloader is not written to the Boot Flash memory?
SoC FPGA
SoC EDS/DS-5
Category: SoCs
Tool: SoC EDS
Device: Cyclone® V
This is expected behavior.
The Watchdog Timer is enabled in the internal BootROM and monitors until the Preloader starts correctly.
If the Preloader image is not in the Boot Flash memory, the Watchdog Timer will periodically repeat the Warm Reset.
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