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Intel: Are there any restrictions on burst access (R/W) on the Avalon-MM bus? (AXI bus must not cross 4KByte address boundaries... etc.)
Category: Quartus® Prime (Platform Designer)
Tools: Quartus® Prime
Device: ー
The Avalon-MM bus standard has no restrictions on address boundaries.
However, depending on the connected master/slave component, there are some restrictions on the address boundary as part of the component specification, so please use it according to the specification of the connected component.
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