Category: External memory interface
Tools: Quartus® Prime
Device: Arria® 10


The basic rules are as follows.

• DQS pins are positioned within one DQ/DQS group (byte lane)
• Free to swap DQ bit positions within one DQ/DQS group (byte lane)
• DQ/DQS groups are assigned to byte lanes (4lane/1bank) of banks used in units of 1 group (1 data byte), but the combination of assignments is free.
• For Address/Command, the pins used within one bank (48 pins) are almost decided (except for some parts that change when the number of Chip select changes)

For protocols that form 8-bit DQ/DQS groups in DDR3/4, execute (set) View ⇒ Show ⇒ Show DQ/DQS Pins ⇒ x8/x9 Mode in the Pin Planner function of Quartus® Prime to set the DQ/DQS groups. Place the differential DQS signals at the pair positions indicated by (S)(~S) after using the color coding.