Narrow down by specifying conditions
There are currently 4292 hits.
Intel: How can I make the area (circuit blocks used by the kernel) smaller?
OpenCL
Category: OpenCL™
Tools: Intel® FPGA SDK for OpenCL™
Device: Cyclone® V
Please refer to the document below for an explanation of area optimization.
Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/opencl-sdk/aocl-best-practices-guide.pdf
(Section of Strategies for Optimizing FPGA Area Usage)
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.