Intel: Is it possible to reset the two CPU cores (Core0, Core1) of the Hard Processor System (HPS) of Arria® V SoC / Cyclone® V SoC separately?

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Intel: Is it possible to reset the two CPU cores (Core0, Core1) of the Arria® V SoC / Cyclone® V SoC Hard Processor System (HPS) separately?

SoC FPGAs

Category: SoCs
Tool: SoC EDS
Device: Arria® V, Cyclone® V

When resetting with an external signal, Core0 and Core1 cannot be reset separately.

Only one core can be reset if it is reset by register control from HPS software.
However, it is only possible to reset Core1 by software control of Core0, or reset Core1 (self) from Core1.
(The configuration in which Core0, which controls the reset, resets itself is deprecated.)

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