Intel: Please tell me how to connect the HPS-to-FPGA AXI Master interface signal of SoC FPGA to the Slave inside Platform Designer (formerly Qsys) and export it externally as AXI.

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Intel: Please tell me how to connect the signal of the HPS-to-FPGA AXI Master interface of the SoC FPGA to the Slave inside Platform Designer (formerly Qsys) and export it to the outside as AXI.

SoC FPGAs

Category: SoCs
Tools: Quartus® Prime (Platform Designer)
Device: Cyclone® V

It is possible by using the AXI Bridge included in the IP catalog of Platform Designer (formerly Qsys).
Connect HPS-to-FPGA Master to Slave of AXI Bridge, and export Master side of AXI Bridge to use.

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