Intel: Are there any samples that show how to do timing constraints when using SPI Core that can be selected from the IP Catalog in Platform Designer (formerly Qsys)?

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Intel: Is there an example showing how to constrain timing when using the SPI Core available from the IP Catalog in Platform Designer (formerly Qsys)?

platform designer

Category: Timing Constraint/Analysis
Tools: Quartus® Prime (Platform Designer)
device:-

If the sample design uses the FPGA side as the SPI Master, the information is available on the following site.

(reference)
https://community.intel.com/t5/FPGA-Wiki/Constrain-SPI-Core/ta-p/735358

This is an example when ADIS16209 made by Analog Devices is connected as a slave device.

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