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Intel: How are the unused pins of the Hard Processor System (HPS) configured in Cyclone® V SoC / Arria® V SoC?

SoC FPGAs

Category: Specifications
Tools: Quartus® Prime
Device: Cyclone® V


Depends on the Unused Pins setting in Quartus® Prime.

Compile in Quartus® Prime with unused pins and check the compilation report.
(Check Compilation Report ⇒ Fitter ⇒ Resource Section ⇒ All Package Pins.)

For unused pin settings, please refer to the following document.

・[Quartus® Getting Started Guide - How to set device options]
https://www.macnica.co.jp/business/semiconductor/articles/intel/95569/

See here for the handling of unused pins in Cyclone® V SoC.

・[Cyclone V GX, GT, E, SX, ST and SE Device Family Pin Connection Guidelines]
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

See here for what to do with unused pins on the Arria® V SoC.

・[Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines]
https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-v/pcg-01013.pdf

Most of the pins are written as below and set the input with a weak pull-up.
If unused, program it in the Quartus Prime software as an input with a weak pull-up.

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