Narrow down by specifying conditions
There are currently 4292 hits.
Intel: What is the test_in setting for PCI Express Hard IP for Straix® V / Arria® V / Cyclone® V?
Category: PCI Express (PCIe)
tool:-
Devices: Stratix® V, Arria® V, Cyclone® V
The following values are recommended for operation on the actual machine.
test_in[31:0] = 32'hA8
See the documentation for settings.
Stratix® V (Avalon-MM)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s5_pcie_avmm.pdf
Stratix® V (Avalon-ST)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s5_pcie_avst.pdf
Arria® V (Avalon-MM)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a5_pcie_avmm.pdf
Arria® V (Avalon-ST)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a5_pcie_avst.pdf
Cyclone® V (Avalon-MM)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf
Cyclone® V (Avalon-ST)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf
(Search for Test Interface Signals.)
Experienced FAE
Free consultation is available.
From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.