I am creating a design using PCI-Express (PCIe) on Intel Cyclone® V using Qsys. When compiling, the following invalid message was found in the SDC for PCIe (altera_pci_express.sdc). Please let me know how to resolve this.

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Intel: Creating designs using PCI-Express (PCIe) with Qsys on Cyclone® V. When compiling, I found the following invalid message in the SDC for PCIe (altera_pci_express.sdc). Please tell me how to deal with it.

Platform Designer PCI Express IP Timing Constraint/Analysis

<Message>
Warning (332174): Ignored filter at altera_pci_express.sdc(16): altpcie_rs_serdes|busy_altgxb_reconfig could not be matched with a register
Warning (332049): Ignored set_false_path at altera_pci_express.sdc(16): Argument <to> is an empty collection
Warning (332174): Ignored filter at altera_pci_express.sdc(16): altpcie_rs_serdes|busy_altgxb_reconfig could not be matched with a register
Warning (332049): Ignored set_false_path at altera_pci_express.sdc(16): Argument <to> is an empty collection

Category: PCI Express
Tools: Quartus® Prime / Quartus® II
Device: Cyclone® V

These warnings are harmless and can be ignored.
There is no busy_altgxb_reconfig inside the Cyclone® V reset controller.
This is the signal name used in devices prior to the 28nm process.

The reset controller currently in use is the Hard Reset Controller (default setting), and users do not need to implement any restrictions.

How to change the reset controller from hard reset to soft reset?
http://www.altera.com/support/kdb/solutions/rd08302012_466.html

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