Intel: When configuring the Hard Processor System (HPS) of Cyclone® V SoC / Arria® V SoC, what is the PLL reference clock frequency item on the SDRAM ⇒ PHY Settings tab on the settings edit screen of Platform Designer (formerly Qsys)? Is it the setting?

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Intel: When setting the Hard Processor System (HPS) of Cyclone® V SoC / Arria® V SoC, what is the PLL reference clock frequency item on the SDRAM ⇒ PHY Settings tab of the configuration edit screen of Platform Designer (formerly Qsys)? settings?

SoCFPGA platform designer

Category: SoCs
Tools: Quartus® Prime / Quartus® II
Device: Cyclone® V / Arria® V

This setting is an item to enter the clock frequency to be input to the PLL of SDRAM.
The clock input to the SDRAM PLL can be selected from 3 systems, and please specify the clock frequency of the selected system.

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