Intel: The L2 Cache of the Hard Processor System (HPS) of the Cyclone® V SoC is composed of a total of 8 ways each 64KB, but is it possible to specify lockdown for a wide address range in multiples of 64KB? ?

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Intel: Cyclone® V SoC's Hard Processor System (HPS) L2 Cache consists of a total of 8 Way units for each 64KB. Is it possible to specify a lockdown for a wide address range in multiples of 64KB? ?

SoC FPGAs

Category: SoCs
Tool: SoC EDS
Device: Cyclone® V

Lockdown is possible in the following units: (Both Way unit and Line unit can be specified)

Line lockdown
Lockdown by way
Lockdown by master (both processors and ACP masters)

See the ARM CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual for details.
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/DDI0246H_l2c310_r3p3_trm.pdf
(Search for Lockdown by way, etc.)

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