Intel: Regarding the PLL of MAX® 10, the documentation states that the clkbad signal is disabled if the frequency difference between inclk0 and inclk1 is more than 20% in Automatic Clock Switchover mode. Is this also true in Manual Clock Switchover mode?

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Intel: For MAX® 10 PLLs, the documentation states that the clkbad signal is invalid if the frequency difference between inclk0 and inclk1 is more than 20% while in Automatic Clock Switchover mode.Is this the same for Manual Clock Switchover mode?

MAX clock/PLL

Category: Specifications
tool:-
Device: MAX®10

This behavior applies only in Automatic Clock Switchover mode, not in Manual Clock Wwichover mode.
The operation of the clkbad signal in Manual Clock Wwichover mode can be confirmed by simulation.

https://www.altera.com/en_US/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf
(See Clock Switchover item.)

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