Intel: MAX® 10 Internal Oscillator frequency variation is listed as Mim 55MHz to Max 116MHz. The SDC automatically generated by the Internal Oscillator contains only Max constraints, but shouldn't Min be considered?
Category: Timing Constraint/Analysis
Tools: Quartus® Prime
Device: MAX®10
Min should also be considered.
Below is an example of additional constraints.
Note that the auto-generated SDC in Quartus® Prime v17.0 is improved.
#original constraint
create_clock -name int_osc_clk -period 8.62 [get_pins -compatibility_mode {*oscillator_dut|clkout}]
#Additional Constraints
create_clock -name int_osc_clk_min -period 18.18 [get_pins -compatibility_mode {*oscillator_dut|clkout}] -add
set_clock_groups -exclusive -group int_osc_clk -group int_osc_clk_min
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