Intel: What is the maximum number of Hard Processor System (HPS) GPIOs that can be used from the FPGA side on the Cyclone® V SoC?

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Intel: What is the maximum number of Hard Processor System (HPS) GPIOs that can be used from the FPGA side in Cyclone® V SoC?

SoC FPGAs

Category: SoCs
Tools: Quartus® Prime
Device: Cyclone® V

It can be confirmed in the Peripherals Mux Table in the HPS parameter Peripheral Pins tab of Platform Designer (formerly Qsys).
Note that there are 6 GCLK input (dedicated) pins on the TOP side, 6 pins dedicated to fPLL output (L), and 16 pins on the Right side.

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