Intel: When using a PLL with a V series FPGA, does the Locked signal toggle during the period from when the reference clock is input until the PLL locks?

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Intel: On V-series FPGAs, when using a PLL, does the Locked signal toggle between the time the reference clock is applied and the PLL locks?

Category: IP (Other)
Tools: Quartus® Prime
Devices: Stratix® V, Arria® V, Cyclone® V

For V-series devices, the Lock signal does not toggle.
There is also information in the following KDB, so please refer to it.

Will the Locked port of the PLL toggle whilst it is in the process of acquiring lock to the input reference clock?
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04282016_719.html

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